Intel's 45nm CMOS Technology

Managing Process Variation in Intel's 45nm CMOS Technology

Kelin Kuhn, Technology and Manufacturing Group, Intel Corporation
Chris Kenyon, Technology and Manufacturing Group, Intel Corporation
Avner Kornfeld, Technology and Manufacturing Group, Intel Corporation
Mark Liu, Technology and Manufacturing Group, Intel Corporation
Atul Maheshwari, Technology and Manufacturing Group, Intel Corporation
Wei-kai Shih, Technology and Manufacturing Group, Intel Corporation
Sam Sivakumar, Technology and Manufacturing Group, Intel Corporation
Greg Taylor, Technology and Manufacturing Group, Intel Corporation
Peter VanDerVoorn, Technology and Manufacturing Group, Intel Corporation
Keith Zawadzki, Technology and Manufacturing Group, Intel Corporation

Index words: 45nm, process variation, DFM

Citations for this paper: Kenyon, C.; Kornfeld, A.; Kuhn, K.; Liu, M.; Maheshwari, A.; Shih, W.; Sivakumar, S.; Taylor, G.; VanDerVoorn, P.; Zawadzki, K. "Managing Process Variation in Intel's 45nm CMOS Technology." Intel Technology Journal. http://www.intel.com/technology/itj/2008/
v12i2/3-managing/1-abstract.htm (June 2008).

ABSTRACT

The key message of this paper is that process variation is not an insurmountable barrier to Moore's Law, but is simply another challenge to be overcome. This message is illustrated with data from the 45nm process generation where process variation is shown to be at least equivalent to (and in many cases better than) process variation in the 65nm- and 90nm-process generations.

We begin this paper with an introduction and historical overview of process variation. Although there has been a trend in recent years to convey process variation as a new challenge associated with advanced CMOS technologies, process variation has been a continuing theme throughout the history of semiconductor process engineering.

We continue with a review of critical sources of variation specific to the 45nm generation, including highly random effects (random dopant fluctuation, line-edge and line-width roughness), variation associated with the gate dielectric (oxide thickness, fixed charge, defects and traps), patterning proximity effects (classical, and those based on optical proximity correction (OPC)), variation associated with polish (shallow-trench isolation, gate, and interconnect), variation associated with strain (wafer-level biaxial, high-stress capping layers, and embedded silicon-germanium (SiGe)), and variation associated with implants and anneals (implant tool-based, implant profile, rapid-thermal anneal, and implant variation associated with poly-grain boundaries).

We then explore the variety of process, design, and layout techniques used in the 45nm generation to mitigate the impact of variation. Pure process mitigation techniques include targeting key transistor properties to reduce random dopant fluctuation, reducing traps at the high-k metal-gate (HiK+MG) interface to reduce random charge variation, improving patterning techniques to reduce line-edge roughness and endcap variation, and improving polishing technologies to reduce systematic cross-wafer variation. Combination design-process techniques include optimizing topology, using OPC to reduce random and systematic variation, and adding dummy features to reduce systematic variation. Pure design techniques include chopping techniques to compensate for random variation and common-centroid layout techniques to compensate for systematic variation.

We move on to illustrate the success of these mitigation techniques by reviewing detailed data characterizing variation in the 45nm generation. Three different types of measurements are presented to illustrate various variation mechanisms. The first is in-fab measurement of variation, used to characterize gate dimensional variation for the 45nm versus 65nm and 90nm generations. The second is low-frequency electrical measurement of matched transistor pairs, used to extract random variation for 45nm versus 65nm transistors. The third is measurements of product ring oscillators, used to determine both systematic and random within-wafer and within-die variation for 45nm versus 65nm products.

Finally, we reinforce the key message that variation does not pose an insurmountable barrier to Moore's Law, but is simply another challenge to be overcome.

Back to Top