Original 45nm Intel® Core™ Microarchitecture

Power Management Enhancements in the 45nm Intel® Core™ Microarchitecture

AUTHORS’ BIOGRAPHIES

Jose Allarey
Jose Allarey joined Intel in 1998 and is currently working as a Computer Architect in the Mobility Group at the Folsom Design Center. His areas of specialization are Power and Thermal Management. He has six patents pending in this area. He received a B.S. degree in Electrical Engineering from the University of the Philippines in 1992 and an M.S. degree in Computer Architecture from Purdue University in 1998. His email is jose.p.allarey at intel.com.

Varghese George
Varghese George is a Principal Engineer in Intel's Mobility Group. He currently leads the MG-US Architecture team. For the Penryn family of processors, he led the PowerThermal Management Architecture team. Varghese joined Intel in 1993 and has worked on various processor products in areas of microarchitecture, multi-processor performance analysis, and power management. His focus in the last few projects has been on power-management techniques on-chip, and he has been instrumental in architecting many key power-management features into Intel processors. He holds more than 15 patents in various domains and has more pending. Varghese holds a B.S. degree in Electrical Engineering from the University of Mysore in India and an M.S. degree in Computer Engineering from the University of Maryland, College Park. His email is varghese.george at intel.com.

Sanjeev Jahagirdar
Sanjeev Jahagirdar joined Intel in 1996 and is currently working as a Computer Architect in the Mobility Group at the Folsom Design Center. His areas of specialization are power and thermal management. He holds seven patents in this area and has more pending. He received a B.S. degree in Electrical Engineering from the College of Engineering, Poona, India; in 1992 and an M.S. degree in Computer Architecture from Arizona State University in 1996. His email is sanjeev.jahagirdar at intel.com.

Glossary

C1—Autohalt state

C1E—Enhanced Autohalt state

C3—Deep Sleep state

C3E—Enhanced Deep Sleep state

C4—Deeper Sleep state

C4E—Enhanced Deeper Sleep state

C5—Enhanced Deeper Sleep state

C6—Deep Power Down state

CC—Core level C state. For example, CC3 is a core-level Deep Sleep state

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