Original 45nm Intel® Core™ Microarchitecture

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Mobility Thin and Small Form-Factor Packaging for Intel® Processors Based on Original 45nm Intel Core™ Microarchitecture

INTRODUCTION

The Intel® processor, originally referred to by the codename Penryn, is the first 45nm processor that is based on Intel Core™ microarchitecture that uses multicore-on-die design to maximize performance and minimize power consumption. It is also the first “all-green” Intel 45nm processor product that is lead and halide free. Historically, Intel mobility processors were packaged in a 35-mm×35-mm substrate, in eight layers of package routing, with a z-height of 2.89mm, on a socket, and with a pin pitch of 1.27mm. This footprint and z-height were design targets for the Penryn mobility processor family. During the life cycle of the Penryn family of processors, two major packaging design requirements were introduced. First, a cost reduction target was identified for the Penryn family of processors. The team responded with innovative designs implementing both six- and four-layer packages, compared to the traditional eight-layer package. Second, a customer requirement was introduced for a smaller and thinner package option. The team was able to leverage the lower-layer-count proposal in order to achieve the new requirement profile. This new package design required a processor package z-height of less than 2mm, with a footprint of 22mm×22mm, a pin pitch of 0.952mm, and a pinmap, supporting the High Density Interconnect (HDI) board. The reduction of the package footprint size meant packing all the signals within the smaller package with negligible additional crosstalk. The challenges of such a design resides in processor power delivery, due to the lower number and placement of package capacitors in the available space constraints. In both cases, the design team was faced with the challenge of fitting a robust core power-delivery system, with negligible performance impact, into a package smaller than the traditional mobility packages.

The Penryn mobility processor with a 3-MB cache form-factor was the first processor in this family to be packaged into the lowest possible package stackup; and with a 6-MB cache, was the first mainstream Small Form Factor (SFF) mobility product to tape out a package in just nine weeks with pinmap redefinition and bottom-up package design. In this paper, we provide an overview of how the Penryn family of processors’ mobility platform and package design teams delivered the Penryn silicon in smaller and thinner packages that enabled customers to design both smaller and thinner form-factor platforms. We provide insight into the mechanical and electrical challenges of these families of thin and SFF packages without incurring significant performance degradation. We also explain how design team members, located across multiple geographical areas, synchronized their work for maximum productivity to achieve multiple package design breakthroughs in mobility package design.

  Section 2 of 10  

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