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- Addressing the Challenges of Tera-scale Computing
Addressing the Challenges of
Tera-scale Computing
The Intel Technology Journal, Volume 13, Issue 4 reports on the progress of the Intel® Tera-scale Computing Research Program at Intel. The content architect for this edition is Jim Held PhD. Intel Fellow and Director of Tera-scale Computing Research at Intel Labs.
In order to accelerate the shift from frequency to parallelism for performance improvement the Intel researchers worldwide are already working on R&D projects to address the hardware and software challenges of building and programming systems with teraFLOPS of parallel performance that can process tera-bytes of data. This level of performance will enable exciting new and emerging applications, but will also require addressing challenges in everything from program architecture to circuit technologies. This issue of the Intel Technology Journal includes results from a range of research that walks down the “stack” from application design to circuits.
Stuart Douglas
Intel Technology Journal Program Manager
Table of Contents
- Foreword
- A Design Pattern Language for Engineering (Parallel) Software
- Hardware and Software Approaches for Deterministic Multi-processor Replay of Concurrent Programs
- A Programming Model for Heterogeneous Intel® x86 Platforms
- Flexible and Adaptive On-chip Interconnect for Tera-scale Architectures
- Tera-scale Memory Challenges and Solutions
- Ultra-low Voltage Technologies for Energy-efficient Special-purpose Hardware Accelerators
- Lessons Learned from the 80-core Tera-scale Research Processor