Intel Technology Journal

A Design Pattern Language for Engineering (Parallel) Software

Wed, 30 Dec 2009 02:15:53 PDT

In this article, we develop our thesis about the central role played by the software architecture.

Hardware and Software Approaches for Deterministic Multi-processor Replay of Concurrent Programs

Wed, 30 Dec 2009 02:15:53 PDT

In this article, we explore hardware and software avenues for improving the programmability of Intel(R) multi-processors.

A Programming Model for Heterogeneous Intel(R) x86 Platforms

Wed, 30 Dec 2009 02:15:53 PDT

The client computing platform is moving towards a heterogeneous architecture that consists of a combination of cores focused on scalar performance, and of a set of throughput-oriented cores.

Flexible and Adaptive On-Chip Interconnect for Tera-scale Architectures

Wed, 30 Dec 2009 02:15:53 PDT

In this article we present the design of an on-chip interconnect with aggressive latency, bandwidth, and energy characteristics that is also flexible and adaptive.

Tera-scale Memory Challenges and Solutions

Wed, 30 Dec 2009 02:15:53 PDT

This article describes the challenges that tera-scale computing presents to the memory sub-system, such as performance metrics including memory bandwidth capacity and latency, as well as the physical challenges of packaging and memory channel design.

Ultra-low Voltage Technologies for Energy-efficient Special-purpose Hardware Accelerators

Wed, 30 Dec 2009 02:15:53 PDT

This article describes ultra-low voltage design techniques and learnings from a video motion estimation engine fabricated in 65nm CMOS technology.

Lessons Learned from the 80-core Tera-scale Research Processor

Wed, 30 Dec 2009 02:15:53 PDT

Sustained tera-scale-level performance within an affordable power envelope is made possible by an energy-efficient, power-managed simple core, and by a packet-switched, two-dimensional mesh network on a chip.